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DDC_DUC
- 数字上下变频FPGA设计的详细介绍资料,还是中文的。很舍不得上传的哦。-FPGA digital down conversion design detailed information, or Chinese. Oh, very reluctant to upload.
DDCFPGA
- 针对DVB-T标准ETSI EN 300 744 V1.5.1,设计了可用于DVB-T接收整机的多速率DDC模块,并在FPGA中仿真实现.在复用数字振荡混频模块的基础上,根据输入信号的不同带宽(6M/8MHz)选择不同的抽取滤波器组完成抽取因子为3或4的多速率处理任务,利用两级半带滤波器(HBF)级联完成4倍抽取滤波,单级奈奎斯特滤波器完成3倍抽取滤波.-For the DVB-T standard ETSI EN 300 744 V1.5.1, designed for DVB-T recei
dspddc_R12p1
- 基于DSPbuilder搭建的DDC,里面包括CIC滤波器,FIR低通滤波器,HB半带滤波器,NCO等,实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
pci_23
- this is 1553B encoder logic writen in verilog. is compatible with 1553 DDC
ddc_filter
- 基于数字下变频的低通滤波器设计,原理和设计理念-digital down convert or ddc low digital filter design
ddc8chou
- 8倍抽取的DDC模块。verilog写的,调试通过-failed to translate
gsm_ddc
- 基于GSM的数字下变频代码,能够直接生成Verilog代码,需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.